1. Field of the Invention
The present invention relates generally to semiconductor memory devices and a testing method thereof, and more particularly, to a semiconductor memory device which can be tested in a simple manner and to a testing method thereof.
2. Description of the Background Art
With the advance of manufacturing techniques of semiconductor integrated circuits and the users' requirements for reducing their prices, the degree of integration of semiconductor memory devices has been increased by about four times in about three years, and presently a dynamic random access memory (referred to as DRAM hereinafter) having capacity of 4M bit has been put to practical use.
In such a DRAM, we consider a testing time when, for example, the following test is performed. First, data of "0" is written in all the memory cells and data of "0" is read out from all memory cells. Then, the same is performed to data of "1" in 10 .mu. sec of cycle time. This cycle time corresponds to a maximum pulse width of a row address strobe signal RAS. The testing time T1 in this case is represented by the following equation (1). EQU T1=4.times.4.times.10.sup.6 .times.10 .mu.sec=160 sec (1)
In this equation, "4" of the first occurrence corresponds to a writing of "0", a reading of "0", a writing of "1" and a reading of "1". In addition, the next "4.times.10.sup.6 " corresponds to a memory capacity and the last "10" .mu. sec corresponds to a cycle time.
In an ordinary DRAM, the above test needs to be performed in four conditions, namely at maximum value 5.5 V in an operating power supply voltage range, at minimum value 4.5 V in the same, at high temperature 70.degree. C. in an operating temperature range, and at low temperature 0.degree. C. in the same. In this case, testing time T2 is represented by the following equation (2). EQU T2=160 sec..times.4=640 sec. (2)
The above value is extremely long as a testing time of an integrated circuit, which causes productivity to decrease and price to increase.
Furthermore, in practice, there are some cases in which defective portions can not be detected with the above items only. Therefore, it is necessary to perform a test which includes in combination, for example, timing conditions of input signals, an addressing order of address signals, and data patterns written into memory cells and the like. In such a case, the testing time becomes extremely long. The primary object of the present invention is to reduce a testing time of a semiconductor memory device with large capacity such as the above.
First, an example of a general DRAM will be described. FIG. 20 is a block diagram showing an entire structure of a conventional DRAM to which the present invention is also applied. In FIG. 20, a reading portion is indicated and a writing portion is not indicated.
In FIG. 20, in a memory cell array 100, a plurality of memory cells for storing information are arranged in rows and columns. An address buffer 200 receives external address signals A0- An applied to external terminals p0- pn from the external and generates internal address signals. An X decoder 300 decodes the internal address signal from the address buffer 200 and selects a corresponding row in the memory cell array 100. A Y decoder 400 decodes the internal address signal from the address buffer 200 and selects a corresponding row in the memory cell array 100. A sense amplifier and I/O block 500 detects and amplifies information read out from memory cells of a single selected row in the memory cell array 100, and transmits the information selected from those information by the Y decoder 400 to an output amplifier 600. The output amplifier 600 amplifies the information transmitted from the sense amplifier and I/O block 500 and outputs it to an output buffer 700. The output buffer 700 outputs to the external as an output data Dout the information applied from the output amplifier 600.
A control signal generation system 800 receives a column address strobe signal CAS, a row address strobe signal RAS and a writing signal W, applied to external terminals 81-83 and generates various control signals to control the operational timing of each portion.
FIG. 21 is a diagram showing a structure of a memory cell array 100 shown in FIG. 20.
In FIG. 21, a plurality of bit line pairs BL and BL comprise folded bit lines. A plurality of word lines WL are arranged so as to intersect with a plurality of bit line pairs BL and BL. At an intersection of each bit line BL and every other word line WL, a memory cell MC is provided, and at an intersection of each bit line BL and every other word line WL, a memory cell MC is provided.
Precharge/equalize circuits 110 are connected to each bit line pair BL and BL. Each precharge/equalize circuit 10 balances a potential on a corresponding bit line pair BL and BL, and precharges the bit line pairs BL and BL to a predetermined potential V.sub.B. In addition, sense amplifiers 510 are connected to each bit line pair BL and BL. Each sense amplifier 510 is activated in response to a first and a second sense amplifier activating signals .phi.A and .phi.B applied via a first and a second signal lines L1, L2, senses a potential difference on the corresponding bit line pair BL and BL and amplifies it differentially. Each of a plurality of bit line pairs BL, BL is connected to data input/output buses I/O and I/O via transfer gates T1 and T2. A decode signal is applied to each gate of transfer gates T1, T2 from the Y decoder 400. In response to a decode signal from the Y decoder 400, a pair of the transfer gates T1, T2 is turned on selectively, so that the corresponding bit line pair BL, BL is connected to the data input/output buses I/O and I/0.
FIG. 22 is a circuit diagram showing in detail a corresponding portion to a bit line pair BL, BL shown in FIG. 21.
In FIG. 22, a single word line WL and a memory cell MC provided at an intersection of the word line WL and a bit line BL are shown. The memory cell MC includes a selection transistor Qs comprised of n-channel insulated gate field-effect transistor (referred to as a n-FET hereinafter), and a memory capacitance Cs for storing information. One electrode of the memory capacitance Cs is connected to the bit line BL via a storage node Ns and the selection transistor Qs, and the other electrode is connected to a ground line. A gate electrode of the selection transistor Qs is connected to the word line WL.
The bit line pair BL and BL are connected to a power supply line L3 via n-FETs Q1 and Q2. A constant voltage V.sub.B that is about half of a power supply potential V.sub.cc is applied to the power supply line L3. When a logical or "H" level precharge signal .phi.p is applied to the gates of n-FETs Q1 and Q2 via a signal line 4, the bit line pair BL, BL are precharged to the potential V.sub.B. Further, a n-FET Q3 is connected between the bit lines BL and BL. At the beginning of stand-by, when a "H" level equalizing signal .phi.e is applied to a gate of the n-FET Q3 via a signal line L5, a potential on the bit line pair BL, BL is balanced.
On the other hand, the sense amplifier 510 includes p-channel insulated gate field-effect transistors (referred to as a p-FET hereinafter) Q4 and Q5 and n-FET Q6 and Q7. The p-FET Q4 is connected between the first signal line L1 receiving a sense amplifier activating signal .phi.A and the bit line BL, and the p-FET Q5 is connected between the first signal line L1 and the bit line BL. Further, the n-FET Q6 is connected between the bit line BL and the second signal line L2 receiving a sense amplifier activating signal .phi.B, and the n-FET Q7 is connected between the bit line BL and the second signal line L2. Gates of the p-FET Q4 and the n-FET Q6 are connected to the bit line BL, and gates of the p-FET Q5 and the n-FET Q7 are connected to the bit line BL.
Between the bit line BL, BL and ground lines, there are parastic capacitances C1 and C2, respectively . The first signal line L1 is connected to a terminal for receiving a power supply potential V.sub.cc via a p-FET Q8, and the second signal line L2 is connected to a ground line via a n-FET Q9. A sense amplifier driving signal .phi.s for controlling a timing operation of a sense amplifier is applied to a gate of the p-FET Q8, and a sense amplifier driving signal .phi.s for controlling a timing operation of a sense amplifier is applied to a gate of the n-FETQ9.
The potential V.sub.B is usually held at 1/2.V.sub.cc. Voltage V.sub.TP is a threshold voltage of the p-FETs Q4 and Q5 and voltage V.sub.TN is a threshold voltage of the n-FETs Q6 and Q7.
Next, referring to a timing chart shown in FIG. 23, an operation of the DRAM in FIG. 20 to FIG. 22 will be explained. In FIG. 23, it is assumed that information of a logical "1" is stored in the memory cell MC and the logical "1" information stored in a memory cell MC is read out.
During the time period from the time t0 to t1, the n-FET Q1- Q3 are turned on. Thus, the bit line pair BL and BL is coupled to the power supply line L3, so that its potential is hold at V.sub.B (=V.sub.cc /2) and the potential between the bit lines BL and BL is balanced. At that time, potentials of the first and the second signal lines L1, L2 for activating the sense amplifier 510 are held at V.sub.cc /2+.vertline.V.sub.TP .vertline. and V.sub.cc /2-V.sub.TN, respectively.
At the time of t2, the precharge signal .phi.p and the equalizing signal .phi.e attain the "L" level, thereby causing the n-FETs Q1 and Q2 to turn off. At the time of t3, when a word line driving signal R rises and is applied to the selected word line WL, the selection transistor Qs is turned on, and a charge stored in the storage node Ns moves onto the bit line BL. As a result, the potential on the bit line BL rises a little (V). The amount of change of the voltage (V) is determined by a capacitance value of the memory capacitance Cs, a capacitance value of a parastic capacitance C1 of the bit line BL and a storage voltage of the storage node Ns by capacitive voltage division as is well understood, which amount (V) is usually about 100-200 mV.
Next, at the time of t4, the sense amplifier driving signal .phi.s rises and the sense amplifier driving signal .phi.s falls. Thus the p-FET Q8 and n-FET Q9 are turned on, so that the potential of the first signal line L1 starts rising and the potential of the second signal line L2 starts falling. Due to the rise and fall of the potential on the first and the second signal lines L1 and L2, a flip-flop circuit comprising the p-FETs Q4 and Q5 and the n-FET Q6 and Q7 starts a sense amplifier operation. As a result, the small potential difference V between the bit lines BL and BL is amplified. The rise of the potential of the bit line BL by V causes a n-FET Q7 to be turned on. As a result, the charge stored in the parasitic capacitance C2 of the bit line BL is discharged via the n-FET Q7, the second signal line L2 and the n-FET Q9, so that the potential of the bit line BL becomes about 0 V at the time of t5.
On the other hand, the fall of the potential of the bit line BL causes the p-FET Q4 to be turned on. As a result, the potential of he bit line BL rises to the V.sub.cc level. Therefore, the potential of the storage node Ns attains the high level (V.sub.cc - V.sub.TN) again, so that a logic level of the storage node Ns is reproduced.
The foregoing is a series of operations of reading information from the memory cell MC, amplifying and reproducing the information. When this series of operations terminates, the DRAM enters a stand-by state in preparation for a next operation.
First, at the time of t8, when a potential of the word line WL falls due to the fall of the word line driving signal R, the selection transistor Qs is turned off. Thus, the memory cell MC enters a stand-by state.
At the time of t10, sense amplifier driving signals .phi.s, .phi.s start falling and rising, respectively, and then at the time of t11, attain the "L" level, and the "H" level, respectively. Thus, the p-FET Q8 and n-FET Q9 are turned off. Further, at the time of t12, the equalizing signal .phi.e starts rising, thus causing the n-FETQ3 to be turned on so that the bit lines BL and BL are coupled to each other. As a result, a charge moves from the high level potential bit line BL to the low level potential bit line BL, and at the time of about t13, both the bit lines BL and BL attain the same potential V.sub.B (=V.sub.cc /2) At the same time, movement of charge occurs between the first and the second signal lines L1 and L2 in high impedance state and the bit lines BL and BL. As a result, the potential levels of the first and the second signal lines Lq, L2 become V.sub.cc /2+.vertline.V.sub.TP.vertline., V.sub.cc /2-V.sub.TN, respectively.
At the time of t14, the precharge signal .phi.p starts rising. Thus, n-FETs Q1 and Q2 are turned on and the bit line pair BL, BL is coupled to the power supply line L3. As a result, the potential level of the bit line pair BL, BL is stabilized and the DRAM waits for the next reading operation.
FIG. 24 is a circuit diagram showing a conventional clock generation circuit for generating a sense amplifier driving signal .phi.s in response to a word line driving signal R. Meanwhile, the word line driving signal R is a signal for rising a potential of the word line selected by an X decoder.
The clock generation circuit includes a plurality of inverter circuits 12-1- 12-n. The plurality of inverter circuits 12-1- 12-n are connected in series between an input terminal I1 and an output terminal O1. Each of the inverter circuits 12-1- 12-n includes a p-FET Q10 and a n-FET Q11 connected in series between a power supply terminal v1 and a ground line via a connecting point N1.
When the word line driving signal R is applied to the input terminal I1, the signal is inverted sequentially by the inverters 12-1- 12-n, and is outputted from the output terminal O1 as the sense amplifier driving signal s. A time difference between the word line driving signal R and the sense amplifier driving signal .phi.s is determined by the sum of a signal propagation delay time (referred to as a delay time hereinafter) in each inverter circuit 12-1- 12-n. In accordance with a required time difference between the word line driving signal R and the sense amplifier signal .phi.s, the number of the inverter circuits and a delay time of each of the inverter circuits are selected. The delay time is provided, for example, by a modification of the FET transmission conductance (gm) by changing sizes of gate width FETs Q10 and Q11.
FIG. 25 is a waveform diagram explaining timing of the word line driving signal R and the sense amplifier driving signal .phi.s, and a potential change of the bit line BL and the second signal line L2.
Now it is assumed that, data of "0" is to be read out from the memory cell MC in FIG. 22. In FIG. 25, at the time of t0, when the word line driving signal R rises to the "H" level, a potential of the selected word line WL attains the "H" level. When the word line driving signal R reaches the threshold voltage VTN of the n-FET, the selection transistor Qs in the memory cell MC conducts and the data stored in the memory cell MC is read out onto the bit line BL. In this case, since the memory cell MC is assumed to store the data of "0", a potential of the storage node Ns in the memory cell MC is 0 V. Thus, following the conductance of the selection transistor Qs, a charge moves from the bit line BL set at 1/2.V.sub.cc level to the storage node Ns. As a result, the potential of the bit line BL decreases. The decreasing rate of the potential of the bit line BL is determined by a transfer conductance of the selection transistor Qs and a capacitance value of the memory capacitance Cs, which is relatively slow.
If the operation of the sense amplifier 510 is started at the timing when the potential of the bit line BL falls down as low as possible, its operation will be more stable. However, if the starting time is late, an operational speed of the DRAM becomes slower. Therefore, at an appropriate time t1 which is later by about 20 ns than the time t0, the sense amplifier driving signal .phi.s is applied. At the time t1, when the sense amplifier driving signal .phi.s reaches the threshold value voltage V.sub.TN, the n-FET Q9 (FIG. 22) starts conducting and a potential of the second signal line L2 starts decreasing. Thus, an operation of the sense amplifier 510 is started and a potential of the bit line BL decreases as the potential of the second signal line L2 decreases. Thus, the signal on the bit line BL is amplified.
As described above, it is preferred that a delay time from the time t0 to the time t1 is shorter in order to increase an operational rate of the DRAM. The main factor for determining the delay time is an electric imbalance existing between the bit lines BL and BL. The electric imbalance is caused by, for example, a difference of a threshold voltage between the n-FETs Q6 and Q7 shown in FIG. 22, a difference of a noise voltage applied from the adjacent circuits to the bit lines BL and BL, and the like. If an operation of a sense amplifier is started at a time when a reading voltage from a memory cell exceeds a sum of imbalance value represented by voltage, an accurate amplifying operation is performed.
Since it is difficult to precisely evaluate such a limiting point of the time at which a sense amplifier does not malfunction, the time is in practice determined experimentally. However, such a time limit at which sense amplifier does not malfunction differs depending on conditions such as an accessing order, and a combination of data of "1" and "0". As it is generally difficult to find limits under all conditions through experiment, the time tl is in practice provided later than a time limit obtained through experiment.
FIG. 26 is an expanded diagram of FIG. 25 for facilitating the understanding of the above description. However, a waveform diagram of a potential of a second signal line L2 is not shown.
In FIG. 26, the times t20-t22 are time limits for an operation of a sense amplifier obtained in various conditions. The time t21 is the time limit obtained under the easiest condition and the time t22 is the time limit obtained under the toughest condition. However, these time limits are simply based on assumption, and only a certain time between the time t21 and the time t22 can be obtained experimentally. In FIG. 26, the time t20 is the typical time limit. In this way, the time t2 will in practice have a range of values. The above description is based on the assumption that properties of a plurality of memory cells are equal.
To the contrary, in a DRAM having a number of memory cells such as 4M bit memory, due to defects caused by dust and the like mixed during manufacturing process, a threshold voltage of a selection transistor in a memory cell sometimes becomes extremely high. In this case, a transfer conductance of a selection transistor decreases so that a potential of a bit line decreases at a slower rate. As a result, such time limit for which a sense amplifier does not malfunction is long.
The times t30-t32 show such time limit as a sense amplifier does not operate erroneously in the presence of a defective memory cell. The problem is that the time t1 when a sense amplifier practically performs an amplifying operation is a little earlier than the time t32 of a time limit obtained under the toughest condition. In this case, depending on the conditions of data stored in adjacent memory cells and the like, a DRAM may or may not operate normally. The toughest condition is caused usually due to a combination of various conditions and it is very difficult for manufacturers to detect it within a limited time.
As a result, a DRAM having such defective memory cells is used by users. Therefore, when used in practice under a particular condition, the problem of an error operation of a DRAM exists.